100G PAM4 vs 100G NRZ

100G Ethernet does not use only one signaling architecture. Earlier 100G optical solutions commonly built the aggregate rate from four 25G-class NRZ lanes, while newer 100G interfaces can use PAM4 to carry the full data stream with fewer, faster lanes. Both approaches target 100GbE, but they place different demands on electrical interfaces, optical components and signal processing.

The key distinction is how many bits are carried by each symbol and how the 100G data rate is distributed across the lanes. NRZ uses two signal levels and one bit per symbol, while PAM4 uses four signal levels and two bits per symbol. This changes the required baud rate, signal margin, FEC requirements, optical architecture and the way 100G connects to higher-speed 200G, 400G and beyond platforms.

1. 100G PAM4 vs 100G NRZ at a Glance

2. What Is 100G NRZ?

100G NRZ describes a 100GbE implementation in which the signaling uses two voltage or optical amplitude levels. Each symbol represents one binary bit.

One common architecture builds the 100G aggregate rate from four 25G-class lanes. Examples of 100G optical interfaces based on four-lane NRZ architectures include 100GBASE-PSM4 and 100G CWDM4-type implementations.

This approach became widely used because 25G-class SerDes and optical lanes were practical for early generations of 100G networking.

3. What Is 100G PAM4?

100G PAM4 refers to a 100G implementation using four-level pulse amplitude modulation. Four distinct amplitude states allow each symbol to encode two bits.

This makes it possible to increase the amount of information carried per symbol without increasing the baud rate by the same factor as a two-level system.

100GBASE-DR, 100GBASE-FR1 and 100GBASE-LR1 are examples of Ethernet interfaces that use 100G-class PAM4 signaling in single-lane optical architectures.

4. Why Both Can Deliver 100GbE

The aggregate Ethernet rate does not tell you how the bits are distributed across the physical lanes.

A simplified example is:

100G NRZ ≈ 4 × 25G-class lanes

100G PAM4 ≈ 1 × 100G-class lane

The exact physical signaling rates include protocol overhead, FEC and implementation details, but the basic principle is that PAM4 carries two bits per symbol while NRZ carries one.

5. Symbol Rate and Bandwidth Efficiency

NRZ requires a higher number of symbols to transmit the same amount of information because each symbol carries only one bit.

PAM4 improves information density by carrying two bits in every symbol. A 50G-class PAM4 lane can therefore deliver roughly twice the bit rate of a 25G-class NRZ lane while remaining in a similar baud-rate range.

For 100G single-lane PAM4, the symbol rate rises into a much higher range, but the two-bits-per-symbol principle remains the same.

6. Signal Levels and Eye Openings

NRZ uses two signal levels and produces one eye opening. PAM4 uses four levels and creates three eye openings.

Because the available amplitude range is divided into more levels, PAM4 has smaller individual eye openings. This reduces the effective vertical noise margin and makes accurate signal generation and detection more challenging.

As a result, PAM4 generally places greater demands on transmitter linearity, receiver performance and equalization.

7. Signal Integrity: NRZ vs PAM4

The simpler two-level structure of NRZ makes it relatively easier to distinguish a logical 0 from a logical 1 when noise and distortion are present.

PAM4 has more closely spaced amplitude levels, so the receiver must distinguish among four states. Crosstalk, reflections, insertion loss, nonlinear behavior and other channel impairments can therefore have a larger impact on the received signal.

This is one of the main engineering trade-offs behind the move from NRZ to PAM4.

8. FEC and Error Performance

Forward Error Correction becomes increasingly important as signaling moves to higher speeds and more complex modulation formats. PAM4's tighter signal margins make error correction especially relevant in many 100G PAM4 interfaces.

FEC can recover data affected by transmission errors and improve the overall link performance. The exact FEC type and whether FEC is mandatory depend on the Ethernet interface and physical-layer specification.

For this reason, a 100G PAM4 transceiver should not be evaluated by optical power and reach alone; its FEC mode is also part of the link design.

9. Electrical Interface and SerDes Architecture

100G NRZ architectures commonly divide the traffic across four 25G-class electrical lanes. This approach aligns naturally with earlier 25G SerDes technologies.

PAM4 allows more information to be transmitted per electrical lane, reducing the number of lanes needed for a given aggregate bandwidth. This makes PAM4 especially useful as switch ASICs and optical modules move toward higher-speed SerDes generations.

The electrical lane structure of the host port must therefore match the optical module and its internal gearbox or lane conversion architecture.

10. Optical Transceiver Architecture

The difference between the two signaling formats is reflected in the optical module itself.

A four-lane NRZ 100G optical transceiver may use four optical transmit and receive lanes, depending on the design. A 100G PAM4 single-lane interface can use one much faster optical lane or another architecture specified for the particular standard.

This can reduce the number of optical lanes and simplify some aspects of higher-density optical connectivity, although the electrical and DSP requirements become more demanding.

11. 100G NRZ Examples

These architectures were important in the early expansion of 100GbE because four 25G-class lanes could be combined into a 100G interface using technologies that were already practical for data center networking.

12. 100G PAM4 Examples

These interfaces illustrate the role of PAM4 in reducing the number of physical lanes required to deliver a 100G-class optical connection.

13. Optical Reach Is Not Determined by Modulation Alone

PAM4 versus NRZ does not by itself determine how far a 100G optical transceiver can transmit. Reach also depends on wavelength, laser technology, transmitter output power, receiver sensitivity, fiber attenuation, dispersion, FEC and the overall optical budget.

For example, different 100G PAM4 interfaces can target different reaches, while several 100G NRZ products also have different optical distances.

The modulation format should therefore be treated as one part of the transceiver design rather than as a direct measure of transmission distance.

14. Power Consumption and Thermal Design

Power consumption varies according to the optical architecture, DSP functions, laser technology, gearbox implementation and module generation.

PAM4 can reduce the number of high-speed lanes required for a given aggregate bandwidth, but it may require more advanced signal processing and tighter electrical design. The final power consumption of a 100G PAM4 module therefore cannot be predicted from modulation format alone.

For high-density switches, the module's actual power rating and thermal behavior should be checked against the host system limits.

15. Cost and Network Migration

100G NRZ technology can benefit from mature four-lane 25G components and established optical designs. PAM4 can offer a more efficient lane architecture but may require newer SerDes, DSP and optical components.

The economic impact depends on the complete system. A network upgrade may also need to consider switch ASIC support, port configuration, breakout options, optical module inventory and compatibility with existing fiber infrastructure.

16. 100G PAM4 vs 100G NRZ Applications

17. How to Select Between 100G PAM4 and 100G NRZ

18. 100G PAM4 vs 100G NRZ: Summary

100G PAM4 and 100G NRZ can both support 100GbE, but they achieve the aggregate data rate through different signaling and lane strategies. NRZ uses two levels and one bit per symbol, while PAM4 uses four levels and two bits per symbol.

Traditional 100G NRZ architectures commonly combine four 25G-class lanes, making them closely aligned with earlier 25G SerDes and established optical modules. 100G PAM4 can reduce the number of physical lanes and is particularly useful for single-lane 100G interfaces and newer high-speed networking architectures.

The trade-off is increased signal complexity. PAM4 provides higher information density per symbol but has smaller eye openings and places greater demands on signal integrity, equalization, FEC and receiver design.

For an actual deployment, the choice should be based on the supported Ethernet interface, host SerDes, optical reach, fiber type, FEC, power consumption and interoperability rather than simply choosing PAM4 or NRZ by modulation format.

19.100G PAM4 vs 100G NRZ Q&A